Frequency-to-digital converters (FDCs) are used in a variety of applications in which a digital representation of the frequency of an electrical signal is needed. For example, they are commonly used in radio frequency (RF) communications transmitters to upconvert communications signals to RF.
As illustrated in FIG. 1, a typical FDC 102 samples an input signal x(t) of unknown frequency fx according to a sample clock s(t) of known frequency fs, to generate a digital stream u(t) containing a sequence of logic ‘1’s and ‘0’s having a density or pattern of logic ‘1’s compared to logic ‘0’s that provides an indication of the ratio of the instantaneous frequencies of the two signals. In applications where a numeric representation of the input signal x(t) is required, a digital filter 104 is used to convert the digital stream u(t) at the FDC 102 output into digital words representing a numeric ratio of instantaneous frequencies, i.e., fx/fs. Since the sample clock s(t) frequency fs is known, the frequency fx of the input signal x(t) can be determined from the frequency ratio fx/fs.
FDCs can be constructed in a variety of different ways. FIG. 2 is a schematic diagram of an FDC 200 constructed according to one known approach. The FDC 200 comprises a plurality of D flip-flops Q1-Q22 arranged in a plurality (here, four) rows, first, second, third and fourth AND gates A1-A4, and a summer. Flip-flops Q7-Q10 and the first AND gate A1 comprise a first positive edge detector in a first row; flip-flops Q11-Q14 and the second AND gate A2 comprise a second positive edge detector in a second row; flip-flops Q15-Q18 and the third AND gate A3 comprise a third positive edge detector in a third row; and flip-flops Q19-Q22 and the fourth AND gate A4 comprise a fourth positive edge detector in a fourth row. Flip-flops Q1 and Q2 operate to divide the input signal x(t) (labeled using its frequency “fx” in FIG. 2) by four, to generate a divided input signal. Flip-flops Q3-Q6 comprise a shift register, which operates to generate four shifted versions (i.e., four input signal phases) of the divided input signal.
The positive edge detectors operate in parallel to asynchronously detect rising (i.e., positive) edges in their respective input signal phases, each outputting a logic ‘1’ for one cycle of the sample clock s(t) (labeled using its frequency “fs” in FIG. 2) for each detected rising edge. The rising edges detected in each of the input signal phases are summed by the summer to form a digital sum representing the ratio of frequencies fx/fs of the input signal x(t) and sample clock s(t). By using four positive edge detectors, the FDC 200 is able to sample an input signal x(t) having a frequency fx up to two times the sample clock frequency fs.
While the above FDC 200 in FIG. 2 is fully capable of converting the frequency of the input signal x(t) to a digital signal representing the input signal's x(t)'s instantaneous frequency, it and other FDCs are known to generate significant amounts of noise during operation. This additive noise reduces the signal-to-noise ratio (SNR) at the FDC output, which can result in suboptimal performance, and in some applications make it difficult, or even impossible, to comply with noise limitation requirements specified by applicable communications standards. It would be desirable, therefore, to have FDC methods and apparatus that offer a better SNR performance than is provided by conventional FDC methods and apparatuses.